During a read operation performed on a flash memory device, a signal generation circuit is generally required to generate a time control signal for allowing read-out of data in a read cycle. Conventionally, the generation of the time control signal is usually accomplished by charging or discharging an RC delay circuit.
Specifically, referring to FIG. 1, which is a schematic circuit diagram of a conventional sensitive amplifier (SA) including a pMOS transistor (P), an nMOS transistor (N) and two inverters (T1 and T2), the pMOS transistor has a drain coupled to an input terminal of the inverter T1, and the inverter T1 has an output terminal that serves as a data output terminal (Dout). A gate of the pMOS transistor is coupled to a time control signal (Precharge). The nMOS transistor has a source coupled to the drain of the pMOS transistor, a drain coupled to an input terminal of the inverter T2 and a gate coupled to an output terminal of the inverter T2, thereby forming a leading inverter. The sensitive amplifier is connected to a test device (Cell) in order to read data therefrom.
FIG. 2 shows a time sequence diagram of the sensitive amplifier circuit performing a data readout operation. At the beginning of the data readout operation, the pMOS transistor is switched on so that a bit-line capacitor (Cbl) or a word-line capacitor (Cwl) of the test device is pre-charged to a threshold voltage of the nMOS transistor. This process requires a time control signal Tpre. After the completion of the pre-charging, the sensitive amplifier circuit performs a current comparison with respect to the level E, i.e., comparing a current Icell flowing in the test device and a reference current Iref. In most cases, Icell is greater than Iref, therefore necessitating the discharge of Icell to a value close to Iref (as indicated by the dashed line in FIG. 2). In other words, the data readout is allowed after the level E is close to zero. Therefore, the data readout cycle requires two time control signals, i.e., Tpre and Twait.
Referring to FIG. 3, which is a schematic diagram of a conventional RC delay circuit, the circuit includes a resistor r, capacitors Cp and Cn and inverters T1 and T2. The RC delay circuit is configured to generate the time control signals Tpre and Twait through charge or discharge of the capacitors.
FIG. 4 is a schematic showing the conventional sensitive amplifier circuit SA (same as the SA circuit shown in FIG. 1) in connection with a test device. Typically, the test device includes a word line decoder (WL_decoder), a bit line decoder (bl_decoder), a word line capacitor (C_wl) and a bit line capacitor (C_bl). Differently-sized test devices have word line capacitors and bit line capacitors with different sizes which require different pre-charge times. That is, Tpre and Twait vary depending on the word line capacitors (C_wl) and the bit line capacitors (C_bl). However, as the RC delay circuit is fabricated with fixed resistor and capacitors values, it is incapable of generating different sets of time control signals Tpre and Twait and thus cannot meet the requirements of different test devices.